This invention relates to a method and a device for testing a sequential circuit. It should be noted here that the term "sequential circuit" means throughout the instant specification a combination of a plurality of registers, namely, memories with a combinational circuit.
It is a recent trend to fabricate a sequential circuit by the large-scale integration technique. A test is indispensable for determining the reliability of a sequential circuit integrated on a large scale to form a multiplicity of registers or memories. During the test of the sequential circuit, the respective registers are connected so that they are operable not only as normal registers in a normal mode but also as a single shift register of cascade connection in a shift mode. The test is automatically executed by the use of a testing device. A conventional testing device puts all the registers in the sequential circuit into operation in the normal and shift modes and derives an external status data set and an internal status data set from the sequential circuit by the use of a preselected test pattern of a multiplicity of test data. The external and internal status data sets are compared with correct patterns prepared in the testing device, respectively, to detect whether or not a fault or defect is present in the sequential circuit. With the conventional testing device, it is difficult to locate a fault in the sequential circuit, as will later be described with reference to one of several figures of the accompanying drawing. All of the test data for the test pattern should be rearranged even when the sequential circuit is partially varied in design. By the way, preparation of the test pattern becomes more difficult with an increase in the number of the registers in the sequential circuit. Therefore, the conventional testing device and method are not useful for testing a sequential circuit of large-scale integration.